changes for oaisim to function with new threading architecture and trx_read/trx_write emulation. Tested for 5/10 MHz TM1. Multiple-antenna mode fails.

usrp 20 MHz on 30.72 master clock. fixed memory leak in prach.c for 20 MHz with 3/4 sampling. added default attributes to threads in lte-enb.c

5ms by default, easy to change (change the 10 in the loops)

if the behavior is worse than before, do git revert [commit ID]

This reverts commit 3f20ce7b.

it was mistakenly pushed to develop