added configuration file for lowband of SoDeRa

changes in lmslib.cpp

changing LOG_E to LOG_W in rx_pucch_emul when UE is not found (this might happen during attach procedure but is ok since nothing will happen)

handling of timing advance is improved. MAC retrieves timing advance from phy once prior to DL scheduling and clears the statistic in PHY. A timer for controlling the timing advance periodicity was introduced.

Limitation of non SI DLSCH allocations in subframe 0/5 to PRBS not around DC (avoid puncturing from PBCH). Placement of SI around DC instead of randomized allocations. Placement of RA allocations at PRB 0-3.  Tested DL throughput on 5 MHz to 16 Mbit/s in TM1.

Added DLSCH scheduling for subframes 0 and 5. Changes in MAC scheduling data structure to keep track of VRB allocations from SI,RA when scheduling regular DLSCH

CCE Allocation in MAC, rebase from develop. Frame number limitation to 1024 for non-real time targets (caused bad bug in oaisim).

The oldest PID (the PID that was used the longest
TTI ago) is at the head and is the next one that
will be used.

No test is done to check that when a process is
allocated it is at least N TTIs old, but some quick
thinking strongly leads to the 'conclusion' that N
won't be smaller than 8, which seems to be what
cat3 UEs require to function properly in the downlink
direction (from the eNodeB to the UE).