Uart code added but not working

firmware/include/common.h

@@ -14,7 +14,9 @@
 //#define DEBUG
 #define REF_VOLTAGE_DIV_BY_ADC_10BITS_RESOLUTION 1.17
 
-#define QUEUE_DIMENSION_UART 20
-#define MESSAGE_DIMENSION 20
+#define QUEUE_DIMENSION_UART 200
+
+#define MESSAGE_DIMENSION 200
+#define  FUNCTION_QUEUE_DIMENSION 2000
 
 #endif /* INCLUDE_COMMON_H_ */

firmware/include/fifo_function_queue.h

@@ -15,11 +15,6 @@
 * Constants shared with other modules
 */
 
-//#define  FUNCTION_QUEUE_DIMENSION 20
-
-//Assert test 1
-#define  FUNCTION_QUEUE_DIMENSION 2
-
 /**
  * @brief Initializes head and tail
  */

firmware/smartwatch/main.c

@@ -18,11 +18,27 @@ void main(void)
 
     //TODO Remove - Crystal configuration
 
-    //Basic Clock System Control Register 1 - Turn off XT2 / ACLK Divider = 1
-    BCSCTL1 = XT2OFF | DIVA_0;
+    PJSEL1 = 0x00;
+    PJSEL0 = 0x08;
 
-    //Basic Clock System Control Register 3 - Use external  32768 Hz crystal for ACLK / capacitance of 12.5pF
-    BCSCTL3 = LFXT1S_0 | XCAP_3;
+    //PJSEL0 = 0x30;  //ISABEL
+
+    //Set HFXTCLK to 48 MHz. SMCLK to 12MHz
+    CS->KEY = CS_KEY_VAL;                                  // Unlock CS module for register access
+    CS->CTL1 = CS_CTL1_DIVS_2 | CS_CTL1_SELS__HFXTCLK | CS_CTL1_SELM__HFXTCLK;  //HFXTCLK for SMCLK and divided by 4.
+    CS->CTL2 = CS_CTL2_HFXTFREQ_6 | CS_CTL2_HFXTDRIVE | CS_CTL2_HFXT_EN;
+
+    CS->CLKEN = CS_CLKEN_SMCLK_EN | CS_CLKEN_HSMCLK_EN;
+
+
+
+    CS -> KEY = 0;
+
+    /*
+    while(CS->IFG& 0x00000002)
+    {
+        CS->CLRIFG= 0x00000002;
+    }*/
 
     initFunctionQueue();
     initializeGPIOModule();
@@ -30,6 +46,7 @@ void main(void)
     initializeBodyTemperature();
     initializeCommunications();
 
+
     __enable_interrupt();
 
 	while(1)
@@ -41,7 +58,7 @@ void main(void)
         }
         else
         {
-            __low_power_mode_3();
+            //__low_power_mode_2();
         }
     }
 

firmware/src/fifo_function_queue.c

 #include "fifo_function_queue.h"
+#include "common.h"
 #include "assert_lab4.h"
 
 static void* function_queue_buffer[FUNCTION_QUEUE_DIMENSION];

firmware/src/gpio.c

@@ -11,7 +11,7 @@ void initializeGPIOModule(void)
     P1OUT = 0;
     P1DIR = 0xE9;
     P1SEL1 = 0;
-    P1SEL0 = 0xE6;
+    P1SEL0 = 0xEC;
 
     P2OUT = 0;
     P2DIR = 0xFF;

firmware/src/uart.c

@@ -20,29 +20,14 @@ void initializeUART()
     EUSCI_A0 -> CTLW0 = EUSCI_A_CTLW0_SWRST;
 
     //Parity disabled, LSB first, 8-bit length, 1 stop bit, asynchronous uart mode
-    //ACLK
-    EUSCI_A0 -> CTLW0 |= EUSCI_A_CTLW0_UCSSEL_1;
-
-
-    //UCA0CTL0 = 0;
-    //UCA0CTL1 |= UCSSEL0;
-
-
-
-
-    //Baud Rate = 9600bps, sourced by ACLK @ 32kHZ
-    //N = frequency of brclk / desired baud rate
-    //UCBR = int(N)
-    //UCBRS = round((N-int(N))*8)
-    UCA0BR0 = 3;
-    UCA0BR1 = 0;
-
-    //Second modulation stage = UCBRSx, Oversampling disabled
-    //UCA0MCTL = UCBRS1 | UCBRS0;
-
+    //SMCLK
+    EUSCI_A0 -> CTLW0 |= EUSCI_A_CTLW0_SSEL__SMCLK;
 
 
 
+    //12MHz to 115200bps
+    EUSCI_A0 -> MCTLW = 0x2000 | 0x0080 | EUSCI_A_MCTLW_OS16;
+    EUSCI_A0 -> BRW = 6;
 
 
     //Configure shared i/o pins
@@ -57,7 +42,7 @@ void initializeUART()
 
     //Turn on the module
     //UCA0CTL1 &= ~UCSWRST;
-    EUSCI_A0 -> CTLW1 &= ~EUSCI_A_CTLW0_SWRST;
+    EUSCI_A0 -> CTLW0 &= ~EUSCI_A_CTLW0_SWRST;
 
     //Enable Interrupts
     //UC0IE = UCA0RXIE;
@@ -135,7 +120,7 @@ void EUSCIA0_IRQHandler(void)
             if(UCA0RXBUF  == '\r')
             {
                 addToFunctionQueue(message_received_callback);
-                __low_power_mode_off_on_exit();
+                //__low_power_mode_off_on_exit();
             }
         }
     }