From cac9ac40415dc9ac42fd21a1a76b07fd4b04c7c3 Mon Sep 17 00:00:00 2001
From: gauthier <lionel.gauthier@eurecom.fr>
Date: Mon, 18 Apr 2016 20:44:30 +0200
Subject: [PATCH] UHD interfacing (master clock 30.72, bandwidths on 5/10/20 @
20 MHz), RX gain calibration back to normal.
---
targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
index aa20a317bb..584e9914ad 100644
--- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
+++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
@@ -617,19 +617,19 @@ extern "C" {
openair0_cfg[0].tx_scheduling_advance = 8*openair0_cfg[0].samples_per_packet;
break;
case 15360000:
- s->usrp->set_master_clock_rate(15.36e06);
+ s->usrp->set_master_clock_rate(30.72e06);
openair0_cfg[0].samples_per_packet = 2048;
openair0_cfg[0].tx_sample_advance = 153;
- openair0_cfg[0].tx_bw = 10e6;
- openair0_cfg[0].rx_bw = 10e6;
+ openair0_cfg[0].tx_bw = 20e6;
+ openair0_cfg[0].rx_bw = 20e6;
openair0_cfg[0].tx_scheduling_advance = 10240;
break;
case 7680000:
- s->usrp->set_master_clock_rate(7.68e6);
+ s->usrp->set_master_clock_rate(30.72e6);
openair0_cfg[0].samples_per_packet = 1024;
- openair0_cfg[0].tx_sample_advance = 103;
- openair0_cfg[0].tx_bw = 5e6;
- openair0_cfg[0].rx_bw = 5e6;
+ openair0_cfg[0].tx_sample_advance = 153;
+ openair0_cfg[0].tx_bw = 20e6;
+ openair0_cfg[0].rx_bw = 20e6;
openair0_cfg[0].tx_scheduling_advance = 5*openair0_cfg[0].samples_per_packet;
break;
case 1920000:
--
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