From a7081fedf72b6567f6bec521cc27df0467bdd6fc Mon Sep 17 00:00:00 2001 From: hongzhi wang <hongzhi.wang@tcl.com> Date: Mon, 4 Jun 2018 17:28:05 +0200 Subject: [PATCH] UE add rf config file --- ...e.band7.tm1.PRB100.NR40.adrv9371-zc706.ini | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini diff --git a/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini new file mode 100644 index 0000000000..8dfe8d6589 --- /dev/null +++ b/targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/ue.band7.tm1.PRB100.NR40.adrv9371-zc706.ini @@ -0,0 +1,89 @@ +[AD9371] +ad9371-phy.in_voltage2_rf_port_select = OFF +ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB +ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB +ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO +ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0 +ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB +ad9371-phy.out_voltage0_quadrature_tracking_en = 1 +ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB +ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0 +ad9371-phy.out_voltage1_quadrature_tracking_en = 1 +ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO +ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000 +ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000 +ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO +ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO +ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO +ad9371-phy.in_voltage0_gain_control_mode = manual +ad9371-phy.in_voltage0_quadrature_tracking_en = 1 +ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB +ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB +ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO +ad9371-phy.in_voltage1_quadrature_tracking_en = 1 +ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB +ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB +ad9371-phy.in_voltage1_gain_control_mode = manual +ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO +ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000 +ad9371-phy.calibrate_rx_qec_en = 0 +ad9371-phy.calibrate_tx_lol_en = 0 +ad9371-phy.calibrate_vswr_en = 0 +ad9371-phy.calibrate_tx_qec_en = 0 +ad9371-phy.calibrate_clgc_en = 0 +ad9371-phy.ensm_mode = radio_on +ad9371-phy.calibrate_tx_lol_ext_en = 0 +ad9371-phy.calibrate_dpd_en = 0 +axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000 +axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160 +axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718 +axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000 +axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000 +axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327 +axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809 +axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000 +axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160 +axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809 +axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0 +axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160 +axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0 +axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000 +axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117 +axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0 +axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000 +axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327 +axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0 +axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160 +axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718 +axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117 +axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1 +axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000 +axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000 +load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR40MHz.txt +dds_mode_tx1 = 1 +dds_mode_tx2 = 1 +dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat +tx_channel_0 = 1 +tx_channel_1 = 1 +tx_channel_2 = 0 +tx_channel_3 = 0 +global_settings_show = 1 +tx_show = 1 +rx_show = 1 +obs_show = 1 +fpga_show = 1 + +[ADRV9371_ZC706] +# NO_DEBUG=0; DEBUG=1 +debug_mode = 0 +# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4 +interpolation_decimation_factor = 1 +# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual" +rx_gain_offset = 43 -- GitLab